Detail CWE-1251

The product's architecture mirrors regions without ensuring that their contents always stay in sync.

Mode Pengenalan

Architecture and Design

Platform yang Berlaku

Bahasa

Nama: VHDL (Undetermined)
Nama: Verilog (Undetermined)

Sistem Operasi

Kelas: Not OS-Specific (Undetermined)

Arsitektur

Kelas: Not Architecture-Specific (Undetermined)

Teknologi

Kelas: System on Chip (Undetermined)

Konsekuensi Umum

Mitigasi yang Memungkinkan

Phases : Architecture and Design

Catatan Pemetaan Kerentanan

Justifikasi : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Komentar : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Catatan

Issues related to state and cache - creation, preservation, and update - are a significant gap in CWE that is expected to be addressed in future versions. It has relationships to concurrency and synchronization, incorrect behavior order, and other areas that already have some coverage in CWE, although the focus has typically been on independent processes on the same operating system - not on independent systems that are all a part of a larger system-of-systems.

Pengajuan

Modifikasi