Detail CWE-1461

The hardware design contains structures that are interpreted differently during synthesis than during simulation, which cause inconsistencies in security-relevant behavior between the synthesized implementation and the simulation.

Mode Pengenalan

Platform yang Berlaku

Bahasa

Nama: Verilog (Undetermined)
Nama: VHDL (Undetermined)
Kelas: Hardware Description Language (Undetermined)

Arsitektur

Kelas: Not Architecture-Specific (Undetermined)

Teknologi

Kelas: System on Chip (Undetermined)

Konsekuensi Umum

Contoh yang Diamati

Mitigasi yang Memungkinkan

Metode Deteksi

Automated Static Analysis - Source Code

Efektivitas : Moderate

Manual Analysis

Efektivitas : Limited

Formal Verification

Efektivitas : High

Simulation / Emulation

Efektivitas : High

Fuzzing

Efektivitas : High

Catatan Pemetaan Kerentanan

Justifikasi : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Komentar : Since this entry is often resultant, there might be other CWEs that are more appropriate as the root cause, although there might be some gaps. Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Referensi

REF-1552

RTL Coding Styles That Yield Simulation and Synthesis Mismatches
Don Mills, Clifford E. Cummings.
https://www.researchgate.net/profile/Clifford-Cummings/publication/228554783_RTL_Coding_Styles_That_Yield_Simulation_and_Synthesis_Mismatches/links/54bfe9760cf21674ce9ca726/RTL-Coding-Styles-That-Yield-Simulation-and-Synthesis-Mismatches.pdf

REF-1553

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Venkat Nitin Patnala, Swarup Bhunia, Sai Manoj P. D..
https://arxiv.org/abs/2504.18812

REF-1554

The Dangers of Living with an X (bugs hidden in your Verilog)
Mike Turpin.
https://developer.arm.com/documentation/arp0009/a/?lang=en

REF-1555

Standard Gotchas: Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know
Stuart Sutherland, Don Mills.
https://sutherland-hdl.com/papers/2006-SNUG-Boston_standard_gotchas_paper.pdf

REF-1556

Lost in Translation: Enabling Confused Deputy Attacks on EDA Software with TransFuzz
Flavien Solt, Kaveh Razavi.
https://www.usenix.org/conference/usenixsecurity25/presentation/solt

REF-1557

Yet Another Latch and Gotchas Paper
Don Mills.
https://lcdm-eng.com/papers/snug12_Paper_final.pdf

REF-1558

“full_case parallel_case”, the Evil Twins of Verilog Synthesis
Clifford E. Cummings.
https://csg.csail.mit.edu/6.375/6_375_2009_www/papers/cummings-case-snug99.pdf

Pengajuan