CWE-1209
Failure to Disable Reserved Bits
2020-02-24
00h00 +00:00
00h00 +00:00
Notifiche per un CWE specifico
Rimani informato su qualsiasi modifica relativa a un CWE specifico.
Nome: Failure to Disable Reserved Bits
The reserved bits in a hardware design are not disabled prior to production.
General Informations
Background Details
Modes Of Introduction
Array : The Designer and Implementer have to make a conscious choice to do this. Designers might covertly use reserved bits to debug or further develop new capabilities in production hardware. Designers might want to use these bits to debug or control/configure a future capability to help minimize time to market (TTM).Documentation : If documentation labels anything "for future use", "reserved", or the like, such labeling could indicate to an attacker a potential attack point.
Piattaforme applicabili
Linguaggio
Classe: Not Language-Specific (Undetermined)Sistemi operativi
Classe: Not OS-Specific (Undetermined)Architetture
Classe: Not Architecture-Specific (Undetermined)Tecnologie
Classe: System on Chip (Undetermined)Conseguenze comuni
| Ambito | Impatto | Probabilità |
|---|---|---|
| Confidentiality Integrity Availability Access Control Accountability Authentication Authorization Non-Repudiation | Varies by Context Nota: If the logic being controlled by these bits is still enabled in production, an adversary could use the logic to induce unwanted/unsupported behavior in the hardware. Adversaries with access to these bits will write to them in hopes of compromising hardware state. This type of weakness all depends on the capabilities of the logic being controlled or configured by the reserved bits. |
Potential Mitigations
Phases : Architecture and Design // ImplementationPhases : Integration
Note sulla mappatura delle vulnerabilità
Giustificazione : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.Commento : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
Pattern di attacco correlati
| CAPEC ID | Nome del pattern di attacco |
|---|---|
| CAPEC-121 | Exploit Non-Production Interfaces
|
Invio
| Nome | Organizzazione | Data | Data di rilascio | Version |
|---|---|---|---|---|
| Brent Sherman | Intel Corporation | 4.0 |
Modifiche
| Nome | Organizzazione | Data | Commento |
|---|---|---|---|
| CWE Content Team | MITRE | updated Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Potential_Mitigations | |
| CWE Content Team | MITRE | updated Demonstrative_Examples | |
| CWE Content Team | MITRE | updated Demonstrative_Examples | |
| CWE Content Team | MITRE | updated Relationships | |
| CWE Content Team | MITRE | updated Mapping_Notes | |
| CWE Content Team | MITRE | updated Weakness_Ordinalities | |
| CWE Content Team | MITRE | updated Background_Details, Common_Consequences, Description, Modes_of_Introduction, Time_of_Introduction |
