CWE-1251 Detail

The product's architecture mirrors regions without ensuring that their contents always stay in sync.

Modes Of Introduction

Architecture and Design

Piattaforme applicabili

Linguaggio

Name: VHDL (Undetermined)
Name: Verilog (Undetermined)

Sistemi operativi

Class: Not OS-Specific (Undetermined)

Architetture

Class: Not Architecture-Specific (Undetermined)

Tecnologie

Class: System on Chip (Undetermined)

Conseguenze comuni

Potential Mitigations

Phases : Architecture and Design

Note sulla mappatura delle vulnerabilità

Giustificazione : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Commento : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Note

Issues related to state and cache - creation, preservation, and update - are a significant gap in CWE that is expected to be addressed in future versions. It has relationships to concurrency and synchronization, incorrect behavior order, and other areas that already have some coverage in CWE, although the focus has typically been on independent processes on the same operating system - not on independent systems that are all a part of a larger system-of-systems.

Invio

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