CWE-1252 Detail

CWE-1252

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
2020-02-24
00h00 +00:00
Incomplete
2026-10-28
00h00 +00:00
CWE Mitre.org
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Gestione notifiche

Nome: CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

The CPU is not configured to provide hardware support for exclusivity of write and execute operations on memory. This allows an attacker to execute data from all of memory.

General Informations

Background Details

Modes Of Introduction

Architecture and Design : If the CPU does not have an MMU/MPU, then there is no write exclusivity.

Piattaforme applicabili

Linguaggio

Classe: Not Language-Specific (Undetermined)

Sistemi operativi

Classe: Not OS-Specific (Undetermined)

Architetture

Classe: Not Architecture-Specific (Undetermined)

Tecnologie

Nome: Microcontroller Hardware (Undetermined)
Nome: Processor Hardware (Undetermined)

Conseguenze comuni

Ambito Impatto Probabilità
Confidentiality
Integrity		Execute Unauthorized Code or Commands

Nota: Without configuring exclusivity of operations via segregated areas of memory, an attacker may be able to inject malicious code onto memory and later execute it.

Potential Mitigations

Phases : Architecture and Design
Phases : Integration

Note sulla mappatura delle vulnerabilità

Giustificazione : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Commento : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Pattern di attacco correlati

CAPEC ID Nome del pattern di attacco
CAPEC-679 Exploitation of Improperly Configured or Implemented Memory Protections

Riferimenti

REF-1076

Cortex-R4 Manual
ARM.
https://developer.arm.com/Processors/Cortex-M4

REF-1077

MCS 51 Microcontroller Family User's Manual
Intel.
http://web.mit.edu/6.115/www/document/8051.pdf

REF-1078

Memory Protection Unit (MPU)
ARM.
https://web.archive.org/web/20200630034848/https://static.docs.arm.com/100699/0100/armv8m_architecture_memory_protection_unit_100699_0100_00_en.pdf

Invio

Nome Organizzazione Data Data di rilascio Version
Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi Intel Corporation 2020-02-13 +00:00 2020-02-24 +00:00 4.0

Modifiche

Nome Organizzazione Data Commento
CWE Content Team MITRE 2020-08-20 +00:00 updated Related_Attack_Patterns
CWE Content Team MITRE 2022-04-28 +00:00 updated Applicable_Platforms, Related_Attack_Patterns
CWE Content Team MITRE 2022-06-28 +00:00 updated Applicable_Platforms
CWE Content Team MITRE 2023-04-27 +00:00 updated References, Relationships
CWE Content Team MITRE 2023-06-29 +00:00 updated Mapping_Notes
CWE Content Team MITRE 2025-12-11 +00:00 updated Common_Consequences, Description, Weakness_Ordinalities
CWE Content Team MITRE 2026-10-28 +00:00 updated Background_Details, Description, Modes_of_Introduction
Le informazioni presentate su CVE Find provengono da diverse fonti di riferimento attentamente selezionate. I dati CVE sono forniti da MITRE Corporation e dal National Vulnerability Database (NVD). Il catalogo delle vulnerabilità sfruttate conosciute (KEV) proviene dalla Cybersecurity and Infrastructure Security Agency (CISA), mentre i punteggi EPSS provengono da FIRST.org. Inoltre, i dati relativi alle vulnerabilità software (CWE) e ai pattern di attacco comuni (CAPEC) sono mantenuti da MITRE Corporation, e le informazioni sulle configurazioni hardware e software (CPE) sono fornite da NVD.