CWE-1251 詳細

The product's architecture mirrors regions without ensuring that their contents always stay in sync.

導入モード

Architecture and Design

適用可能なプラットフォーム

言語

名前： VHDL (Undetermined)
名前： Verilog (Undetermined)

オペレーティングシステム

クラス： Not OS-Specific (Undetermined)

アーキテクチャ

クラス： Not Architecture-Specific (Undetermined)

テクノロジー

クラス： System on Chip (Undetermined)

一般的な結果

潜在的な緩和策

Phases : Architecture and Design

脆弱性マッピングノート

理由 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
コメント : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

ノート

Issues related to state and cache - creation, preservation, and update - are a significant gap in CWE that is expected to be addressed in future versions. It has relationships to concurrency and synchronization, incorrect behavior order, and other areas that already have some coverage in CWE, although the focus has typically been on independent processes on the same operating system - not on independent systems that are all a part of a larger system-of-systems.

登録情報

変更履歴