名前: Improper Handling of Overlap Between Protected Memory Ranges

The product allows address regions to overlap, which can result in the bypassing of intended memory protection.

一般情報

導入モード

Architecture and Design : Such issues could be introduced during hardware architecture and design or implementation and identified later during the Testing phase.
Implementation

適用可能なプラットフォーム

言語

クラス： Not Language-Specific (Undetermined)

オペレーティングシステム

クラス： Not OS-Specific (Undetermined)

アーキテクチャ

クラス： Not Architecture-Specific (Undetermined)

テクノロジー

名前： Memory Hardware (Undetermined)
名前： Processor Hardware (Undetermined)

一般的な結果

スコープ	影響	可能性
Confidentiality Integrity Availability	Modify Memory, Read Memory, DoS: Instability, DoS: Prevent Access	High

観察された例

参考文献	説明
CVE-2008-7096	virtualization product allows compromise of hardware product by accessing certain remapping registers.
[REF-1100]	processor design flaw allows ring 0 code to access more privileged rings by causing a register window to overlap a range of protected system RAM [REF-1100]

潜在的な緩和策

Phases : Architecture and Design
Phases : Implementation

検出方法

Manual Analysis

Create a high privilege memory block of any arbitrary size. Attempt to create a lower privilege memory block with an overlap of the high privilege memory block. If the creation attempt works, fix the hardware. Repeat the test.
有効性 : High

脆弱性マッピングノート

理由 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
コメント : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

ノート

As of CWE 4.6, CWE-1260 and CWE-1316 are siblings under view 1000, but CWE-1260 might be a parent of CWE-1316. More analysis is warranted.

参考文献

登録情報

名前	組織	日付	リリース日	Version
Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi	Intel Corporation	2020-02-10 +00:00	2020-02-24 +00:00	4.1

変更履歴

名前	組織	日付	コメント
CWE Content Team	MITRE	2020-08-20 +00:00	updated Demonstrative_Examples, Description, Modes_of_Introduction, Related_Attack_Patterns
CWE Content Team	MITRE	2020-12-10 +00:00	updated Maintenance_Notes
CWE Content Team	MITRE	2021-10-28 +00:00	updated Demonstrative_Examples, Description, Detection_Factors, Maintenance_Notes, Observed_Examples, Relationships, Weakness_Ordinalities
CWE Content Team	MITRE	2022-04-28 +00:00	updated Applicable_Platforms, Related_Attack_Patterns
CWE Content Team	MITRE	2022-06-28 +00:00	updated Applicable_Platforms
CWE Content Team	MITRE	2023-01-31 +00:00	updated Related_Attack_Patterns
CWE Content Team	MITRE	2023-04-27 +00:00	updated Relationships
CWE Content Team	MITRE	2023-06-29 +00:00	updated Demonstrative_Examples, Mapping_Notes, References
CWE Content Team	MITRE	2025-09-09 +00:00	updated Relationships
CWE Content Team	MITRE	2026-10-28 +00:00	updated Common_Consequences, Demonstrative_Examples, Description

CAPEC ID	攻撃パターン名
CAPEC-456	Infected Memory An adversary inserts malicious logic into memory enabling them to achieve a negative impact. This logic is often hidden from the user of the system and works behind the scenes to achieve negative impacts. This pattern of attack focuses on systems already fielded and used in operation as opposed to systems that are still under development and part of the supply chain.
CAPEC-679	Exploitation of Improperly Configured or Implemented Memory Protections

CWE-1260 詳細

CWE-1260