CWE-1296 詳細

CWE-1296

Incorrect Chaining or Granularity of Debug Components
2020-08-20
00h00 +00:00
Incomplete
2026-10-28
00h00 +00:00
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名前: Incorrect Chaining or Granularity of Debug Components

The product's debug components contain incorrect chaining or granularity of debug components.

一般情報

背景の詳細

導入モード

Implementation : Logic errors during design or synthesis could misconfigure the interconnection of the debug components, which could allow unintended access permissions.

適用可能なプラットフォーム

言語

名前: Verilog (Undetermined)
名前: VHDL (Undetermined)
クラス: Not Language-Specific (Undetermined)

オペレーティングシステム

クラス: Not OS-Specific (Undetermined)

アーキテクチャ

クラス: Not Architecture-Specific (Undetermined)

テクノロジー

名前: Processor Hardware (Undetermined)
クラス: Not Technology-Specific (Undetermined)

一般的な結果

スコープ 影響 可能性
Confidentiality
Integrity
Access Control
Authentication
Authorization
Availability
Accountability
Gain Privileges or Assume Identity, Bypass Protection Mechanism, Execute Unauthorized Code or Commands, Modify Memory, Modify Files or Directories

注記:Depending on the access to debug component(s) erroneously granted, an attacker could use the debug component to gain additional understanding about the system to further an attack and/or execute other commands. This could compromise any security property, including the ones listed above.
Medium

観察された例

参考文献 説明

CVE-2017-18347

Incorrect access control in RDP Level 1 on STMicroelectronics STM32F0 series devices allows physically present attackers to extract the device's protected firmware via a special sequence of Serial Wire Debug (SWD) commands because there is a race condition between full initialization of the SWD interface and the setup of flash protection.

CVE-2020-1791

There is an improper authorization vulnerability in several smartphones. The system has a logic-judging error, and, under certain scenarios, a successful exploit could allow the attacker to switch to third desktop after a series of operations in ADB mode. (Vulnerability ID: HWPSIRT-2019-10114).

潜在的な緩和策

Phases : Implementation
Ensure that debug components are properly chained and their granularity is maintained at different authentication levels.

検出方法

Architecture or Design Review

Appropriate Post-Si tests should be carried out at various authorization levels to ensure that debug components are properly chained and accessible only to users with appropriate credentials.
有効性 : High

Dynamic Analysis with Manual Results Interpretation

Appropriate Post-Si tests should be carried out at various authorization levels to ensure that debug components are properly chained and accessible only to users with appropriate credentials.
有効性 : High

脆弱性マッピングノート

理由 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
コメント : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

関連する攻撃パターン

CAPEC ID 攻撃パターン名
CAPEC-121 Exploit Non-Production Interfaces
CAPEC-702 Exploiting Incorrect Chaining or Granularity of Hardware Debug Components

ノート

This entry is still under development and will continue to see updates and content improvements.

登録情報

名前 組織 日付 リリース日 Version
Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna Intel Corporation 2020-05-31 +00:00 2020-08-20 +00:00 4.2

変更履歴

名前 組織 日付 コメント
CWE Content Team MITRE 2021-07-20 +00:00 updated Related_Attack_Patterns
CWE Content Team MITRE 2022-04-28 +00:00 updated Applicable_Platforms, Related_Attack_Patterns
CWE Content Team MITRE 2022-06-28 +00:00 updated Applicable_Platforms
CWE Content Team MITRE 2023-01-31 +00:00 updated Related_Attack_Patterns
CWE Content Team MITRE 2023-04-27 +00:00 updated Relationships
CWE Content Team MITRE 2023-06-29 +00:00 updated Mapping_Notes
CWE Content Team MITRE 2025-12-11 +00:00 updated Weakness_Ordinalities
CWE Content Team MITRE 2026-10-28 +00:00 updated Background_Details, Description, Modes_of_Introduction