導入モード
Architecture and Design
Implementation
Requirements
適用可能なプラットフォーム
言語
名前: C (Undetermined)
名前: C++ (Undetermined)
名前: Verilog (Undetermined)
クラス: Hardware Description Language (Undetermined)
クラス: Not Language-Specific (Undetermined)
アーキテクチャ
名前: ARM (Undetermined)
名前: x86 (Undetermined)
クラス: Embedded (Undetermined)
テクノロジー
名前: Security Hardware (Undetermined)
名前: Processor Hardware (Undetermined)
名前: Microcontroller Hardware (Undetermined)
クラス: System on Chip (Undetermined)
一般的な結果
| スコープ |
影響 |
可能性 |
| Confidentiality | Read Memory, Read Files or Directories | Medium |
| Integrity | Modify Memory, Modify Files or Directories | Medium |
| Availability | DoS: Resource Consumption (Memory), DoS: Crash, Exit, or Restart | High |
観察された例
| 参考文献 |
説明 |
| Open source silicon root of trust (RoT) product does not immediately report when an integrity check fails for memory requests, causing the product to accept and continue processing data [REF-1468] |
潜在的な緩和策
Phases : Architecture and Design
Phases : Implementation
検出方法
Automated Static Analysis - Source Code
有効性 : High
Manual Static Analysis - Source Code
有効性 : Moderate
脆弱性マッピングノート
理由 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
コメント : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
参考文献
REF-1468
OpenTitan issue: [rv_core_ibex] Bus errors on integrity check failure
GregAC.
https://github.com/lowRISC/opentitan/issues/11336
登録情報
| 名前 |
組織 |
日付 |
リリース日 |
Version |
| Amisha Srivastava |
University of Texas at Dallas |
2023-12-20 +00:00 |
2025-04-03 +00:00 |
4.17 |
変更履歴
| 名前 |
組織 |
日付 |
コメント |
| CWE Content Team |
MITRE |
2025-12-11 +00:00 |
updated Demonstrative_Examples, Weakness_Ordinalities |
| CWE Content Team |
MITRE |
2026-10-28 +00:00 |
updated Demonstrative_Examples, Detection_Factors |