CWE-1476
Improper Request Propagation before Data Reception in Write Transactions in a Bus Architecture
2026-10-28
00h00 +00:00
00h00 +00:00
Incomplete
特定のCWEの通知
特定のCWEの変更情報をいち早くお届けします。
名前: Improper Request Propagation before Data Reception in Write Transactions in a Bus Architecture
The product uses a multi-manager shared bus architecture
with an on-chip interconnect that speculatively propagates
a request for a write transaction, but it does not ensure
that the remaining steps required by the manager module to
complete the request are fulfilled in a timely manner.
一般情報
背景の詳細
導入モード
適用可能なプラットフォーム
言語
クラス： Not Language-Specific (Undetermined)アーキテクチャ
名前： ARM (Undetermined)クラス： Not Architecture-Specific (Undetermined)
テクノロジー
名前： Bus/Interface Hardware (Undetermined)名前： Communication Hardware (Undetermined)
クラス： System on Chip (Undetermined)
一般的な結果
| スコープ | 影響 | 可能性 |
|---|---|---|
| Availability | DoS: Prevent Access | High |
観察された例
| 参考文献 | 説明 |
|---|---|
[REF-1586] | Certain commercial AXI interconnect IPs could allow a manager to cause bus stalls. |
潜在的な緩和策
検出方法
Architecture or Design Review
有効性 : OpportunisticFormal Verification
有効性 : HighSimulation / Emulation
有効性 : Moderate脆弱性マッピングノート
理由 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.コメント : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
参考文献
REF-1585
Cut and Forward: Safe and Secure Communication for FPGA System on ChipsFrancesco Restuccia, Ryan Kastner.
https://ieeexplore.ieee.org/document/9852740
REF-1586
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoCFrancesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgio Buttazzo.
https://ieeexplore.ieee.org/abstract/document/9114758
REF-1587
[AXI-REALM: A lightweight and modular interconnect extension for traffic regulation and monitoring of heterogeneous real-time SoCsThomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini.
https://ieeexplore.ieee.org/document/10546511
REF-1588
Safety verification of third-party hardware modules via information flow trackingAndres Meza, Francesco Restuccia, Ryan Kastner, Jason Oberg.
https://kastner.ucsd.edu/wp-content/uploads/2022/08/admin/rage22-safety.pdf
登録情報
| 名前 | 組織 | 日付 | リリース日 | Version |
|---|---|---|---|---|
| Francesco Restuccia | University of California San Diego | 5.0 |
