CWE-1251 상세 정보

The product's architecture mirrors regions without ensuring that their contents always stay in sync.

취약점 도입 방식

Architecture and Design

적용 가능한 플랫폼

언어

이름: VHDL (Undetermined)
이름: Verilog (Undetermined)

운영 체제

클래스: Not OS-Specific (Undetermined)

아키텍처

클래스: Not Architecture-Specific (Undetermined)

기술

클래스: System on Chip (Undetermined)

일반적인 결과

잠재적 완화 방법

Phases : Architecture and Design

취약점 매핑 메모

근거 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
댓글 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

메모

Issues related to state and cache - creation, preservation, and update - are a significant gap in CWE that is expected to be addressed in future versions. It has relationships to concurrency and synchronization, incorrect behavior order, and other areas that already have some coverage in CWE, although the focus has typically been on independent processes on the same operating system - not on independent systems that are all a part of a larger system-of-systems.

제출

수정 사항