취약점 도입 방식
Architecture and Design
Implementation
Requirements
적용 가능한 플랫폼
언어
이름: C (Undetermined)
이름: C++ (Undetermined)
이름: Verilog (Undetermined)
클래스: Hardware Description Language (Undetermined)
클래스: Not Language-Specific (Undetermined)
아키텍처
이름: ARM (Undetermined)
이름: x86 (Undetermined)
클래스: Embedded (Undetermined)
기술
이름: Security Hardware (Undetermined)
이름: Processor Hardware (Undetermined)
이름: Microcontroller Hardware (Undetermined)
클래스: System on Chip (Undetermined)
일반적인 결과
| 범위 |
영향 |
가능성 |
| Confidentiality | Read Memory, Read Files or Directories | Medium |
| Integrity | Modify Memory, Modify Files or Directories | Medium |
| Availability | DoS: Resource Consumption (Memory), DoS: Crash, Exit, or Restart | High |
관찰된 예시
| 참고 자료 |
설명 |
| Open source silicon root of trust (RoT) product does not immediately report when an integrity check fails for memory requests, causing the product to accept and continue processing data [REF-1468] |
잠재적 완화 방법
Phases : Architecture and Design
Phases : Implementation
탐지 방법
Automated Static Analysis - Source Code
효과성 : High
Manual Static Analysis - Source Code
효과성 : Moderate
취약점 매핑 메모
근거 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
댓글 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
참고 자료
REF-1468
OpenTitan issue: [rv_core_ibex] Bus errors on integrity check failure
GregAC.
https://github.com/lowRISC/opentitan/issues/11336
제출
| 이름 |
조직 |
날짜 |
출시일 |
Version |
| Amisha Srivastava |
University of Texas at Dallas |
2023-12-20 +00:00 |
2025-04-03 +00:00 |
4.17 |
수정 사항
| 이름 |
조직 |
날짜 |
댓글 |
| CWE Content Team |
MITRE |
2025-12-11 +00:00 |
updated Demonstrative_Examples, Weakness_Ordinalities |
| CWE Content Team |
MITRE |
2026-10-28 +00:00 |
updated Demonstrative_Examples, Detection_Factors |