이름: Improper Request Propagation before Data Reception in Write Transactions in a Bus Architecture

The product uses a multi-manager shared bus architecture with an on-chip interconnect that speculatively propagates a request for a write transaction, but it does not ensure that the remaining steps required by the manager module to complete the request are fulfilled in a timely manner.

일반 정보

배경 세부 정보

취약점 도입 방식

적용 가능한 플랫폼

언어

클래스: Not Language-Specific (Undetermined)

아키텍처

이름: ARM (Undetermined)
클래스: Not Architecture-Specific (Undetermined)

기술

이름: Bus/Interface Hardware (Undetermined)
이름: Communication Hardware (Undetermined)
클래스: System on Chip (Undetermined)

일반적인 결과

범위	영향	가능성
Availability	DoS: Prevent Access	High

관찰된 예시

참고 자료	설명
[REF-1586]	Certain commercial AXI interconnect IPs could allow a manager to cause bus stalls.

잠재적 완화 방법

탐지 방법

Architecture or Design Review

효과성 : Opportunistic

Formal Verification

효과성 : High

Simulation / Emulation

효과성 : Moderate

취약점 매핑 메모

근거 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
댓글 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

참고 자료

REF-1585

Cut and Forward: Safe and Secure Communication for FPGA System on Chips
Francesco Restuccia, Ryan Kastner.
https://ieeexplore.ieee.org/document/9852740

REF-1586

Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgio Buttazzo.
https://ieeexplore.ieee.org/abstract/document/9114758

REF-1587

[AXI-REALM: A lightweight and modular interconnect extension for traffic regulation and monitoring of heterogeneous real-time SoCs
Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini.
https://ieeexplore.ieee.org/document/10546511

REF-1588

Safety verification of third-party hardware modules via information flow tracking
Andres Meza, Francesco Restuccia, Ryan Kastner, Jason Oberg.
https://kastner.ucsd.edu/wp-content/uploads/2022/08/admin/rage22-safety.pdf

제출

이름	조직	날짜	출시일	Version
Francesco Restuccia	University of California San Diego	2022-08-25 +00:00	2026-10-28 +00:00	5.0

CWE-1476 상세 정보

CWE-1476