Nazwa: Hardware Allows Activation of Test or Debug Logic at Runtime

During runtime, the hardware allows for test or debug logic (feature) to be activated, which allows for changing the state of the hardware. This feature can alter the intended behavior of the system and allow for alteration and leakage of sensitive data by an adversary.

Informacje ogólne

Sposoby wprowadzenia

Architecture and Design : Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.
Implementation : Such issues could be introduced during implementation and identified later during Testing or System Configuration phases.
Integration : Such issues could be introduced during integration and identified later during Testing or System configuration phases.

Odpowiednie platformy

Język

Klasa: Not Language-Specific (Undetermined)

Systemy operacyjne

Klasa: Not OS-Specific (Undetermined)

Architektury

Klasa: Not Architecture-Specific (Undetermined)

Technologie

Klasa: Not Technology-Specific (Undetermined)

Typowe konsekwencje

Zakres	Wpływ	Prawdopodobieństwo
Confidentiality Integrity Availability	Modify Memory, Read Memory, DoS: Crash, Exit, or Restart, DoS: Instability, DoS: Resource Consumption (CPU), DoS: Resource Consumption (Memory), DoS: Resource Consumption (Other), Execute Unauthorized Code or Commands, Gain Privileges or Assume Identity, Bypass Protection Mechanism, Alter Execution Logic, Quality Degradation, Unexpected State, Reduce Performance, Reduce Reliability Uwaga: An adversary can take advantage of test or debug logic that is made accessible through the hardware during normal operation to modify the intended behavior of the system. For example, an accessible Test/debug mode may allow read/write access to any system data. Using error injection (a common test/debug feature) during a transmit/receive operation on a bus, data may be modified to produce an unintended message. Similarly, confidentiality could be compromised by such features allowing access to secrets.

Zaobserwowane przykłady

Odniesienia	Opis
CVE-2021-33150	Hardware processor allows activation of test or debug logic at runtime.
CVE-2021-0146	Processor allows the activation of test or debug logic at runtime, allowing escalation of privileges

Potencjalne środki zaradcze

Phases : Architecture and Design
Insert restrictions on when the hardware's test or debug features can be activated. For example, during normal operating modes, the hardware's privileged modes that allow access to such features cannot be activated. Configuring the hardware to only enter a test or debug mode within a window of opportunity such as during boot or configuration stage. The result is disablement of such test/debug features and associated modes during normal runtime operations.
Phases : Implementation
Insert restrictions on when the hardware's test or debug features can be activated. For example, during normal operating modes, the hardware's privileged modes that allow access to such features cannot be activated. Configuring the hardware to only enter a test or debug mode within a window of opportunity such as during boot or configuration stage. The result is disablement of such test/debug features and associated modes during normal runtime operations.
Phases : Integration
Insert restrictions on when the hardware's test or debug features can be activated. For example, during normal operating modes, the hardware's privileged modes that allow access to such features cannot be activated. Configuring the hardware to only enter a test or debug mode within a window of opportunity such as during boot or configuration stage. The result is disablement of such test/debug features and associated modes during normal runtime operations.

Uwagi dotyczące mapowania podatności

Uzasadnienie : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Komentarz : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Powiązane wzorce ataków

CAPEC ID	Nazwa wzorca ataku
CAPEC-121	Exploit Non-Production Interfaces

Zgłoszenie

Nazwa	Organizacja	Data	Data wydania	Version
Brent Sherman	Accellera IP Security Assurance (IPSA) Working Group	2020-08-06 +00:00	2020-12-10 +00:00	4.3

Modyfikacje

Nazwa	Organizacja	Data	Komentarz
CWE Content Team	MITRE	2022-04-28 +00:00	updated Related_Attack_Patterns
CWE Content Team	MITRE	2023-04-27 +00:00	updated Relationships
CWE Content Team	MITRE	2023-06-29 +00:00	updated Mapping_Notes
CWE Content Team	MITRE	2023-10-26 +00:00	updated Observed_Examples
CWE Content Team	MITRE	2025-12-11 +00:00	updated Weakness_Ordinalities
CWE Content Team	MITRE	2026-10-28 +00:00	updated Common_Consequences, Description

Szczegóły CWE-1313

CWE-1313