Các cách xuất hiện
Architecture and Design : Optimizations built into the design of the processor can have unintended consequences during the execution of an application.
Nền tảng áp dụng
Ngôn ngữ
Lớp: Not Language-Specific (Rarely)
Công nghệ
Tên: Processor Hardware (Undetermined)
Hậu quả phổ biến
| Phạm vi |
Tác động |
Khả năng xảy ra |
| Integrity | Bypass Protection Mechanism
Ghi chú: A successful exploitation of this weakness will change the order of an application's execution and will likely be used to bypass specific protection mechanisms. This bypass can be exploited further to potentially read data that should otherwise be unaccessible. | High |
Ví dụ đã quan sát
| Tài liệu tham khảo |
Mô tả |
| Intel, ARM, and AMD processor optimizations related to speculative execution and branch prediction cause access control checks to be bypassed when placing data into the cache. Often known as "Spectre". |
| Intel, ARM, and AMD processor optimizations related to speculative execution and branch prediction cause access control checks to be bypassed when placing data into the cache. Often known as "Spectre". |
| Intel processor optimizations related to speculative execution cause access control checks to be bypassed when placing data into the cache. Often known as "Meltdown". |
Phương pháp phát hiện
White Box
In theory this weakness can be detected through the use of white box testing techniques where specifically crafted test cases are used in conjunction with debuggers to verify the order of statements being executed.
Hiệu quả : Opportunistic
Ghi chú ánh xạ lỗ hổng
Lý do : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Bình luận : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
Mẫu tấn công liên quan
| ID CAPEC |
Tên mẫu tấn công |
| CAPEC-663 |
Exploitation of Transient Instruction Execution
An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution to expose sensitive data and bypass/subvert access control over restricted resources. Typically, the adversary conducts a covert channel attack to target non-discarded microarchitectural changes caused by transient executions such as speculative execution, branch prediction, instruction pipelining, and/or out-of-order execution. The transient execution results in a series of instructions (gadgets) which construct covert channel and access/transfer the secret data. |
Ghi chú
As of CWE 4.9, members of the CWE Hardware SIG are closely analyzing this entry and others to improve CWE's coverage of transient execution weaknesses, which include issues related to Spectre, Meltdown, and other attacks. Additional investigation may include other weaknesses related to microarchitectural state. As a result, this entry might change significantly in CWE 4.10.
Tài liệu tham khảo
REF-11
Spectre Attacks: Exploiting Speculative Execution
Paul Kocher, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, Yuval Yarom.
https://arxiv.org/abs/1801.01203 REF-12
Meltdown
Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, Mike Hamburg.
https://arxiv.org/abs/1801.01207
Gửi
| Tên |
Tổ chức |
Ngày |
Ngày phát hành |
Version |
| CWE Content Team |
MITRE |
2018-03-07 +00:00 |
2018-03-29 +00:00 |
3.1 |
Sửa đổi
| Tên |
Tổ chức |
Ngày |
Bình luận |
| CWE Content Team |
MITRE |
2020-02-24 +00:00 |
updated Relationships |
| CWE Content Team |
MITRE |
2020-06-25 +00:00 |
updated Relationships |
| CWE Content Team |
MITRE |
2021-03-15 +00:00 |
updated Related_Attack_Patterns |
| CWE Content Team |
MITRE |
2022-10-13 +00:00 |
updated Applicable_Platforms, Maintenance_Notes |
| CWE Content Team |
MITRE |
2023-04-27 +00:00 |
updated Relationships |
| CWE Content Team |
MITRE |
2023-06-29 +00:00 |
updated Mapping_Notes |
| CWE Content Team |
MITRE |
2026-10-28 +00:00 |
updated Dimensions |