CWE-1252
CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
2020-02-24
00h00 +00:00
00h00 +00:00
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Tên: CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
The CPU is not configured to provide hardware support for exclusivity of write and execute operations on memory. This allows an attacker to execute data from all of memory.
Thông tin chung
Chi tiết nền tảng
Các cách xuất hiện
Architecture and Design : If the CPU does not have an MMU/MPU, then there is no write exclusivity.Nền tảng áp dụng
Ngôn ngữ
Lớp: Not Language-Specific (Undetermined)Hệ điều hành
Lớp: Not OS-Specific (Undetermined)Kiến trúc
Lớp: Not Architecture-Specific (Undetermined)Công nghệ
Tên: Microcontroller Hardware (Undetermined)Tên: Processor Hardware (Undetermined)
Hậu quả phổ biến
| Phạm vi | Tác động | Khả năng xảy ra |
|---|---|---|
| Confidentiality Integrity | Execute Unauthorized Code or Commands Ghi chú: Without configuring exclusivity of operations via segregated areas of memory, an attacker may be able to inject malicious code onto memory and later execute it. |
Các biện pháp giảm thiểu tiềm năng
Phases : Architecture and DesignPhases : Integration
Ghi chú ánh xạ lỗ hổng
Lý do : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.Bình luận : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
Mẫu tấn công liên quan
| ID CAPEC | Tên mẫu tấn công |
|---|---|
| CAPEC-679 | Exploitation of Improperly Configured or Implemented Memory Protections
|
Tài liệu tham khảo
REF-1076
Cortex-R4 ManualARM.
https://developer.arm.com/Processors/Cortex-M4
REF-1077
MCS 51 Microcontroller Family User's ManualIntel.
http://web.mit.edu/6.115/www/document/8051.pdf
REF-1078
Memory Protection Unit (MPU)ARM.
https://web.archive.org/web/20200630034848/https://static.docs.arm.com/100699/0100/armv8m_architecture_memory_protection_unit_100699_0100_00_en.pdf
Gửi
| Tên | Tổ chức | Ngày | Ngày phát hành | Version |
|---|---|---|---|---|
| Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi | Intel Corporation | 4.0 |
Sửa đổi
| Tên | Tổ chức | Ngày | Bình luận |
|---|---|---|---|
| CWE Content Team | MITRE | updated Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Applicable_Platforms, Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Applicable_Platforms | |
| CWE Content Team | MITRE | updated References, Relationships | |
| CWE Content Team | MITRE | updated Mapping_Notes | |
| CWE Content Team | MITRE | updated Common_Consequences, Description, Weakness_Ordinalities | |
| CWE Content Team | MITRE | updated Background_Details, Description, Modes_of_Introduction |
