CWE-1476
Improper Request Propagation before Data Reception in Write Transactions in a Bus Architecture
2026-10-28
00h00 +00:00
00h00 +00:00
Incomplete
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Tên: Improper Request Propagation before Data Reception in Write Transactions in a Bus Architecture
The product uses a multi-manager shared bus architecture
with an on-chip interconnect that speculatively propagates
a request for a write transaction, but it does not ensure
that the remaining steps required by the manager module to
complete the request are fulfilled in a timely manner.
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Nền tảng áp dụng
Ngôn ngữ
Lớp: Not Language-Specific (Undetermined)Kiến trúc
Tên: ARM (Undetermined)Lớp: Not Architecture-Specific (Undetermined)
Công nghệ
Tên: Bus/Interface Hardware (Undetermined)Tên: Communication Hardware (Undetermined)
Lớp: System on Chip (Undetermined)
Hậu quả phổ biến
| Phạm vi | Tác động | Khả năng xảy ra |
|---|---|---|
| Availability | DoS: Prevent Access | High |
Ví dụ đã quan sát
| Tài liệu tham khảo | Mô tả |
|---|---|
[REF-1586] | Certain commercial AXI interconnect IPs could allow a manager to cause bus stalls. |
Các biện pháp giảm thiểu tiềm năng
Phương pháp phát hiện
Architecture or Design Review
Hiệu quả : OpportunisticFormal Verification
Hiệu quả : HighSimulation / Emulation
Hiệu quả : ModerateGhi chú ánh xạ lỗ hổng
Lý do : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.Bình luận : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
Tài liệu tham khảo
REF-1585
Cut and Forward: Safe and Secure Communication for FPGA System on ChipsFrancesco Restuccia, Ryan Kastner.
https://ieeexplore.ieee.org/document/9852740
REF-1586
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoCFrancesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgio Buttazzo.
https://ieeexplore.ieee.org/abstract/document/9114758
REF-1587
[AXI-REALM: A lightweight and modular interconnect extension for traffic regulation and monitoring of heterogeneous real-time SoCsThomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini.
https://ieeexplore.ieee.org/document/10546511
REF-1588
Safety verification of third-party hardware modules via information flow trackingAndres Meza, Francesco Restuccia, Ryan Kastner, Jason Oberg.
https://kastner.ucsd.edu/wp-content/uploads/2022/08/admin/rage22-safety.pdf
Gửi
| Tên | Tổ chức | Ngày | Ngày phát hành | Version |
|---|---|---|---|---|
| Francesco Restuccia | University of California San Diego | 5.0 |
