名稱: Improper Zeroization of Hardware Register

The hardware product does not properly clear sensitive information from built-in registers when the user of the hardware block changes.

一般資訊

背景詳情

引入方式

Architecture and Design : Lack of hardware mechanisms to zeroize or clear registers in the design or specification.
Implementation : Mechanisms to zeroize and clear registers are in the design but implemented incorrectly.
Operation : Hardware-provided zeroization mechanisms are not used appropriately by the IP user (ex. firmware), or data remanence issues are not taken into account.

適用平台

程式語言

類別： Not Language-Specific (Undetermined)

作業系統

類別： Not OS-Specific (Undetermined)

架構

類別： Not Architecture-Specific (Undetermined)

技術

類別： System on Chip (Undetermined)

常見後果

範圍	影響	可能性
Confidentiality	Varies by Context 注意：The consequences will depend on the information disclosed due to the vulnerability. When a different entity obtains access to the IP due to a change in operating mode or conditions, the new entity can extract information belonging to the previous user if no mechanisms are in place to clear register contents.

潛在緩解措施

Phases : Architecture and Design
It is important to clear information stored in the hardware if a physical attack on the product is detected, or if the user of the hardware block changes. Every register potentially containing sensitive information must have a policy specifying how and when information is cleared, in addition to clarifying if it is the responsibility of the hardware logic or IP user to initiate the zeroization procedure at the appropriate time.

漏洞對應備注

理由說明 : This CWE entry is at the Variant level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
備註 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

相關攻擊模式

CAPEC ID	攻擊模式名稱
CAPEC-150	Collect Data from Common Resource Locations An adversary exploits well-known locations for resources for the purposes of undermining the security of the target. In many, if not most systems, files and resources are organized in a default tree structure. This can be useful for adversaries because they often know where to look for resources or files that are necessary for attacks. Even when the precise location of a targeted resource may not be known, naming conventions may indicate a small area of the target machine's file tree where the resources are typically located. For example, configuration files are normally stored in the /etc director on Unix systems. Adversaries can take advantage of this to commit other types of attacks.
CAPEC-204	Lifting Sensitive Data Embedded in Cache An adversary examines a target application's cache, or a browser cache, for sensitive information. Many applications that communicate with remote entities or which perform intensive calculations utilize caches to improve efficiency. However, if the application computes or receives sensitive information and the cache is not appropriately protected, an attacker can browse the cache and retrieve this information. This can result in the disclosure of sensitive information.
CAPEC-37	Retrieve Embedded Sensitive Data An attacker examines a target system to find sensitive data that has been embedded within it. This information can reveal confidential contents, such as account numbers or individual keys/credentials that can be used as an intermediate step in a larger attack.
CAPEC-545	Pull Data from System Resources An adversary who is authorized or has the ability to search known system resources, does so with the intention of gathering useful information. System resources include files, memory, and other aspects of the target system. In this pattern of attack, the adversary does not necessarily know what they are going to find when they start pulling data. This is different than CAPEC-150 where the adversary knows what they are looking for due to the common location.

備注

The process of clearing register contents in a hardware IP is referred to as zeroization in standards for cryptographic hardware modules such as FIPS-140-2 [REF-267].

參考資料

REF-267

FIPS PUB 140-2: SECURITY REQUIREMENTS FOR CRYPTOGRAPHIC MODULES
Information Technology Laboratory, National Institute of Standards and Technology.
https://csrc.nist.gov/files/pubs/fips/140-2/upd2/final/docs/fips1402.pdf

提交

名稱	機構	日期	發布日期	Version
Nicole Fern	Cycuity (originally submitted as Tortuga Logic)	2020-02-08 +00:00	2020-02-24 +00:00	4.0

修改記錄

名稱	機構	日期	備註
CWE Content Team	MITRE	2020-08-20 +00:00	updated Related_Attack_Patterns
CWE Content Team	MITRE	2021-10-28 +00:00	updated Relationships
CWE Content Team	MITRE	2023-04-27 +00:00	updated References, Relationships
CWE Content Team	MITRE	2023-06-29 +00:00	updated Mapping_Notes
CWE Content Team	MITRE	2024-02-29 +00:00	updated Demonstrative_Examples, References
CWE Content Team	MITRE	2025-09-09 +00:00	updated References
CWE Content Team	MITRE	2025-12-11 +00:00	updated Weakness_Ordinalities
CWE Content Team	MITRE	2026-10-28 +00:00	updated Background_Details, Common_Consequences, Demonstrative_Examples, Description, Potential_Mitigations, Relationships, Terminology_Notes

CWE-1239 詳細資料

CWE-1239