CWE-1251 詳細資料

The product's architecture mirrors regions without ensuring that their contents always stay in sync.

引入方式

Architecture and Design

適用平台

程式語言

名稱： VHDL (Undetermined)
名稱： Verilog (Undetermined)

作業系統

類別： Not OS-Specific (Undetermined)

架構

類別： Not Architecture-Specific (Undetermined)

技術

類別： System on Chip (Undetermined)

常見後果

潛在緩解措施

Phases : Architecture and Design

漏洞對應備注

理由說明 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
備註 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

備注

Issues related to state and cache - creation, preservation, and update - are a significant gap in CWE that is expected to be addressed in future versions. It has relationships to concurrency and synchronization, incorrect behavior order, and other areas that already have some coverage in CWE, although the focus has typically been on independent processes on the same operating system - not on independent systems that are all a part of a larger system-of-systems.

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