CWE-1255
Comparison Logic is Vulnerable to Power Side-Channel Attacks
2020-08-20
00h00 +00:00
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指定 CWE 通知
掌握特定 CWE 的任何變更。
名稱: Comparison Logic is Vulnerable to Power Side-Channel Attacks
A device's real time power consumption may be monitored during security token evaluation and the information gleaned may be used to determine the value of the reference token.
一般資訊
引入方式
Architecture and Design : The design of the algorithm itself may intrinsically allow the power side channel attack to be effective.Implementation : This weakness may be introduced during implementation despite a robust design that otherwise prevents exploitation.
適用平台
程式語言
類別： Not Language-Specific (Undetermined)作業系統
類別： Not OS-Specific (Undetermined)架構
類別： Not Architecture-Specific (Undetermined)技術
類別： Not Technology-Specific (Undetermined)常見後果
| 範圍 | 影響 | 可能性 |
|---|---|---|
| Confidentiality Integrity Availability Access Control Accountability Authentication Authorization Non-Repudiation | Modify Memory, Read Memory, Read Files or Directories, Modify Files or Directories, Execute Unauthorized Code or Commands, Gain Privileges or Assume Identity, Bypass Protection Mechanism, Read Application Data, Modify Application Data, Hide Activities 注意：The power consumed by a device may be instrumented and monitored in real time. If the algorithm for evaluating security tokens is not sufficiently robust, the power consumption may vary by token entry comparison against the reference value. Further, if retries are unlimited, the power difference between a "good" entry and a "bad" entry may be observed and used to determine whether each entry itself is correct thereby allowing unauthorized parties to calculate the reference value. As compromising a security token may result in complete system control, the impacts are relatively universal. |
觀察到的案例
| 參考資料 | 描述 |
|---|---|
CVE-2020-12788 | CMAC verification vulnerable to timing and power attacks. |
潛在緩解措施
Phases : Architecture and DesignThe design phase must consider each check of a security token against a standard and the amount of power consumed during the check of a good token versus a bad token. The alternative is an all at once check where a retry counter is incremented PRIOR to the check.
Phases : Architecture and Design
Another potential mitigation is to parallelize shifting of secret data (see example 2 below). Note that the wider the bus the more effective the result.
Phases : Architecture and Design
An additional potential mitigation is to add random data to each crypto operation then subtract it out afterwards. This is highly effective but costly in performance, area, and power consumption. It also requires a random number generator.
Phases : Implementation
If the architecture is unable to prevent the attack, using filtering components may reduce the ability to implement an attack, however, consideration must be given to the physical removal of the filter elements.
Phases : Integration
During integration, avoid use of a single secret for an extended period (e.g. frequent key updates). This limits the amount of data compromised but at the cost of complexity of use.
漏洞對應備注
理由說明 : This CWE entry is at the Variant level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.備註 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
相關攻擊模式
| CAPEC ID | 攻擊模式名稱 |
|---|---|
| CAPEC-189 | Black Box Reverse Engineering
An adversary discovers the structure, function, and composition of a type of computer software through black box analysis techniques. 'Black Box' methods involve interacting with the software indirectly, in the absence of direct access to the executable object. Such analysis typically involves interacting with the software at the boundaries of where the software interfaces with a larger execution environment, such as input-output vectors, libraries, or APIs. Black Box Reverse Engineering also refers to gathering physical side effects of a hardware device, such as electromagnetic radiation or sounds. |
參考資料
REF-1184
Power AnalysisWikipedia.
https://en.wikipedia.org/wiki/Power_analysis
提交
| 名稱 | 機構 | 日期 | 發布日期 | Version |
|---|---|---|---|---|
| CWE Content Team | MITRE | 4.2 |
修改記錄
| 名稱 | 機構 | 日期 | 備註 |
|---|---|---|---|
| CWE Content Team | MITRE | updated Functional_Areas, Maintenance_Notes, Relationships | |
| CWE Content Team | MITRE | updated Demonstrative_Examples, Modes_of_Introduction, Observed_Examples, Potential_Mitigations, References, Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Maintenance_Notes, References, Relationships, Type | |
| CWE Content Team | MITRE | updated Relationships | |
| CWE Content Team | MITRE | updated Demonstrative_Examples | |
| CWE Content Team | MITRE | updated Relationships | |
| CWE Content Team | MITRE | updated Mapping_Notes | |
| CWE Content Team | MITRE | updated Demonstrative_Examples | |
| CWE Content Team | MITRE | updated Weakness_Ordinalities | |
| CWE Content Team | MITRE | updated Common_Consequences, Description |
