名稱: Improper Handling of Overlap Between Protected Memory Ranges

The product allows address regions to overlap, which can result in the bypassing of intended memory protection.

一般資訊

引入方式

Architecture and Design : Such issues could be introduced during hardware architecture and design or implementation and identified later during the Testing phase.
Implementation

適用平台

程式語言

類別： Not Language-Specific (Undetermined)

作業系統

類別： Not OS-Specific (Undetermined)

架構

類別： Not Architecture-Specific (Undetermined)

技術

名稱： Memory Hardware (Undetermined)
名稱： Processor Hardware (Undetermined)

常見後果

範圍	影響	可能性
Confidentiality Integrity Availability	Modify Memory, Read Memory, DoS: Instability, DoS: Prevent Access	High

觀察到的案例

參考資料	描述
CVE-2008-7096	virtualization product allows compromise of hardware product by accessing certain remapping registers.
[REF-1100]	processor design flaw allows ring 0 code to access more privileged rings by causing a register window to overlap a range of protected system RAM [REF-1100]

潛在緩解措施

Phases : Architecture and Design
Phases : Implementation

偵測方法

Manual Analysis

Create a high privilege memory block of any arbitrary size. Attempt to create a lower privilege memory block with an overlap of the high privilege memory block. If the creation attempt works, fix the hardware. Repeat the test.
有效性 : High

漏洞對應備注

理由說明 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
備註 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

備注

As of CWE 4.6, CWE-1260 and CWE-1316 are siblings under view 1000, but CWE-1260 might be a parent of CWE-1316. More analysis is warranted.

參考資料

提交

名稱	機構	日期	發布日期	Version
Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi	Intel Corporation	2020-02-10 +00:00	2020-02-24 +00:00	4.1

修改記錄

名稱	機構	日期	備註
CWE Content Team	MITRE	2020-08-20 +00:00	updated Demonstrative_Examples, Description, Modes_of_Introduction, Related_Attack_Patterns
CWE Content Team	MITRE	2020-12-10 +00:00	updated Maintenance_Notes
CWE Content Team	MITRE	2021-10-28 +00:00	updated Demonstrative_Examples, Description, Detection_Factors, Maintenance_Notes, Observed_Examples, Relationships, Weakness_Ordinalities
CWE Content Team	MITRE	2022-04-28 +00:00	updated Applicable_Platforms, Related_Attack_Patterns
CWE Content Team	MITRE	2022-06-28 +00:00	updated Applicable_Platforms
CWE Content Team	MITRE	2023-01-31 +00:00	updated Related_Attack_Patterns
CWE Content Team	MITRE	2023-04-27 +00:00	updated Relationships
CWE Content Team	MITRE	2023-06-29 +00:00	updated Demonstrative_Examples, Mapping_Notes, References
CWE Content Team	MITRE	2025-09-09 +00:00	updated Relationships
CWE Content Team	MITRE	2026-10-28 +00:00	updated Common_Consequences, Demonstrative_Examples, Description

CAPEC ID	攻擊模式名稱
CAPEC-456	Infected Memory An adversary inserts malicious logic into memory enabling them to achieve a negative impact. This logic is often hidden from the user of the system and works behind the scenes to achieve negative impacts. This pattern of attack focuses on systems already fielded and used in operation as opposed to systems that are still under development and part of the supply chain.
CAPEC-679	Exploitation of Improperly Configured or Implemented Memory Protections

CWE-1260 詳細資料

CWE-1260