CWE-1296
Incorrect Chaining or Granularity of Debug Components
2020-08-20
00h00 +00:00
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指定 CWE 通知
掌握特定 CWE 的任何變更。
名稱: Incorrect Chaining or Granularity of Debug Components
The product's debug components contain incorrect chaining or granularity of debug components.
一般資訊
背景詳情
引入方式
Implementation : Logic errors during design or synthesis could misconfigure the interconnection of the debug components, which could allow unintended access permissions.適用平台
程式語言
名稱： Verilog (Undetermined)名稱： VHDL (Undetermined)
類別： Not Language-Specific (Undetermined)
作業系統
類別： Not OS-Specific (Undetermined)架構
類別： Not Architecture-Specific (Undetermined)技術
名稱： Processor Hardware (Undetermined)類別： Not Technology-Specific (Undetermined)
常見後果
| 範圍 | 影響 | 可能性 |
|---|---|---|
| Confidentiality Integrity Access Control Authentication Authorization Availability Accountability | Gain Privileges or Assume Identity, Bypass Protection Mechanism, Execute Unauthorized Code or Commands, Modify Memory, Modify Files or Directories 注意：Depending on the access to debug component(s) erroneously granted, an attacker could use the debug component to gain additional understanding about the system to further an attack and/or execute other commands. This could compromise any security property, including the ones listed above. | Medium |
觀察到的案例
| 參考資料 | 描述 |
|---|---|
CVE-2017-18347 | Incorrect access control in RDP Level 1 on STMicroelectronics STM32F0 series devices allows physically present attackers to extract the device's protected firmware via a special sequence of Serial Wire Debug (SWD) commands because there is a race condition between full initialization of the SWD interface and the setup of flash protection. |
CVE-2020-1791 | There is an improper authorization vulnerability in several smartphones. The system has a logic-judging error, and, under certain scenarios, a successful exploit could allow the attacker to switch to third desktop after a series of operations in ADB mode. (Vulnerability ID: HWPSIRT-2019-10114). |
潛在緩解措施
Phases : ImplementationEnsure that debug components are properly chained and their granularity is maintained at different authentication levels.
偵測方法
Architecture or Design Review
Appropriate Post-Si tests should be carried out at various authorization levels to ensure that debug components are properly chained and accessible only to users with appropriate credentials.有效性 : High
Dynamic Analysis with Manual Results Interpretation
Appropriate Post-Si tests should be carried out at various authorization levels to ensure that debug components are properly chained and accessible only to users with appropriate credentials.有效性 : High
漏洞對應備注
理由說明 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.備註 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
相關攻擊模式
| CAPEC ID | 攻擊模式名稱 |
|---|---|
| CAPEC-121 | Exploit Non-Production Interfaces
|
| CAPEC-702 | Exploiting Incorrect Chaining or Granularity of Hardware Debug Components
|
備注
This entry is still under development and will continue to see updates and content improvements.提交
| 名稱 | 機構 | 日期 | 發布日期 | Version |
|---|---|---|---|---|
| Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna | Intel Corporation | 4.2 |
修改記錄
| 名稱 | 機構 | 日期 | 備註 |
|---|---|---|---|
| CWE Content Team | MITRE | updated Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Applicable_Platforms, Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Applicable_Platforms | |
| CWE Content Team | MITRE | updated Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Relationships | |
| CWE Content Team | MITRE | updated Mapping_Notes | |
| CWE Content Team | MITRE | updated Weakness_Ordinalities | |
| CWE Content Team | MITRE | updated Background_Details, Description, Modes_of_Introduction |
