引入方式
Architecture and Design
Implementation
Requirements
適用平台
程式語言
名稱: C (Undetermined)
名稱: C++ (Undetermined)
名稱: Verilog (Undetermined)
類別: Hardware Description Language (Undetermined)
類別: Not Language-Specific (Undetermined)
架構
名稱: ARM (Undetermined)
名稱: x86 (Undetermined)
類別: Embedded (Undetermined)
技術
名稱: Security Hardware (Undetermined)
名稱: Processor Hardware (Undetermined)
名稱: Microcontroller Hardware (Undetermined)
類別: System on Chip (Undetermined)
常見後果
| 範圍 |
影響 |
可能性 |
| Confidentiality | Read Memory, Read Files or Directories | Medium |
| Integrity | Modify Memory, Modify Files or Directories | Medium |
| Availability | DoS: Resource Consumption (Memory), DoS: Crash, Exit, or Restart | High |
觀察到的案例
| 參考資料 |
描述 |
| Open source silicon root of trust (RoT) product does not immediately report when an integrity check fails for memory requests, causing the product to accept and continue processing data [REF-1468] |
潛在緩解措施
Phases : Architecture and Design
Phases : Implementation
偵測方法
Automated Static Analysis - Source Code
有效性 : High
Manual Static Analysis - Source Code
有效性 : Moderate
漏洞對應備注
理由說明 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
備註 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
參考資料
REF-1468
OpenTitan issue: [rv_core_ibex] Bus errors on integrity check failure
GregAC.
https://github.com/lowRISC/opentitan/issues/11336
提交
| 名稱 |
機構 |
日期 |
發布日期 |
Version |
| Amisha Srivastava |
University of Texas at Dallas |
2023-12-20 +00:00 |
2025-04-03 +00:00 |
4.17 |
修改記錄
| 名稱 |
機構 |
日期 |
備註 |
| CWE Content Team |
MITRE |
2025-12-11 +00:00 |
updated Demonstrative_Examples, Weakness_Ordinalities |
| CWE Content Team |
MITRE |
2026-10-28 +00:00 |
updated Demonstrative_Examples, Detection_Factors |