CWE-1431 詳細資料

The product uses a hardware module implementing a cryptographic algorithm that writes sensitive information about the intermediate state or results of its cryptographic operations via one of its output wires (typically the output port containing the final result).

引入方式

Implementation

適用平台

程式語言

類別： Not Language-Specific (Undetermined)

架構

類別： Not Architecture-Specific (Undetermined)

技術

類別： System on Chip (Undetermined)

常見後果

潛在緩解措施

Phases : Architecture and Design
Phases : Implementation

偵測方法

Automated Static Analysis - Source Code

有效性 : High

Simulation / Emulation

有效性 : High

Formal Verification

有效性 : High

Manual Analysis

有效性 : Opportunistic

漏洞對應備注

理由說明 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
備註 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

參考資料

REF-1469

OpenTitan issue: [otp_ctrl] Prevent broadcast of scrambler's input/intermediate values #13043
Andres Meza.
https://github.com/lowRISC/opentitan/pull/13043

REF-1470

Security Verification of the OpenTitan Hardware Root of Trust
Andres Meza, Francesco Restuccia, Jason Oberg, Dominic Rizzo, Ryan Kastner.
https://ieeexplore.ieee.org/document/10106105

REF-1471

Security Verification of an Open Source Hardware Root of Trust
Jason Oberg.
https://cycuity.com/type/blog/security-verification-of-an-open-source-hardware-root-of-trust/

REF-1472

Complete reverse-engineering of AES-like block ciphers by SCARE and FIRE attacks
Christophe Clavier, Quentin Isorez, Damien Marion, Antoine Wurcker.
https://doi.org/10.1007/s12095-014-0112-7

REF-1473

Practical Reverse Engineering of Secret Sboxes by Side-Channel Analysis
Dirmanto Jap, Shivam Bhasin.
https://doi.org/10.1109/ISCAS45731.2020.9180848

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