CWE-1224 Details

The hardware design control register "sticky bits" or write-once bit fields are improperly implemented, such that they can be reprogrammed by software.

Einführungsmodi

Architecture and Design
Implementation : Such issues could be introduced during implementation of hardware design, since IP parameters and defaults are defined in HDL code and identified later during Testing or System Configuration phases.

Anwendbare Plattformen

Sprache

Name: Verilog (Undetermined)
Name: VHDL (Undetermined)

Technologien

Class: System on Chip (Undetermined)

Häufige Konsequenzen

Mögliche Gegenmaßnahmen

Phases : Architecture and Design
During hardware design, all register write-once or sticky fields must be evaluated for proper configuration.

Erkennungsmethoden

Automated Analysis

Use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.

Hinweise zur Schwachstellen-Zuordnung

Begründung : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Kommentar : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Verwandte Angriffsmuster

Einreichung

Änderungen