CAPEC-702 详情

执行流程

[Find and scan debug interface] The adversary must first find and scan a debug interface to determine what they are authorized to use and what devices are chained to that interface.

• Use a JTAGulator on a JTAG interface to determine the correct pin configuration, baud rate, and number of devices in the chain

[Connect to debug interface] The adversary next connects a device to the JTAG interface using the properties found in the explore phase so that they can send commands. The adversary sends some test commands to make sure the connection is working.

• Connect a device such as a BusPirate or UM232H to the JTAG interface and connect using pin layout found from the JTAGulator

[Move along debug chain] Once the adversary has connected to the main TAP, or JTAG interface, they will move along the TAP chain to see what debug interfaces might be available on that chain.

• Run a command such as “scan_chain” to see what TAPs are available in the chain.

前提条件

Hardware device has an exposed debug interface

所需技能

Ability to identify physical debug interfaces on a device
Ability to operate devices to scan and connect to an exposed debug interface

所需资源

A device to scan a TAP or JTAG interface, such as a JTAGulator
A device to communicate on a TAP or JTAG interface, such as a BusPirate

缓解措施

Implement: Ensure that debug components are properly chained, and their granularity is maintained at different authorization levels
Perform Post-silicon validation tests at various authorization levels to ensure that debug components are only accessible to authorized users

相关弱点

参考资料

REF-748

Overview of the Test Access Port
Hewlett-Packard Journal.
https://www.hpl.hp.com/hpjournal/94dec/dec94a7a.pdf

REF-749

Finding Faults with the Test Access Port (TAP)
https://flynn.com/2017/06/12/finding-faults-with-the-test-access-port-tap/

REF-750

Technical Guide to JTAG
https://www.xjtag.com/about-jtag/jtag-a-technical-overview/

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