CWE-1262 详情

The product uses memory-mapped I/O registers that act as an interface to hardware functionality from software, but there is improper access control to those registers.

引入方式

Architecture and Design : This weakness may be exploited if the register interface design does not adequately protect hardware assets from software.
Implementation : Mis-implementation of access control policies may inadvertently allow access to hardware assets through the register interface.

适用平台

编程语言

类： Not Language-Specific (Undetermined)

操作系统

类： Not OS-Specific (Undetermined)

架构

类： Not Architecture-Specific (Undetermined)

技术

类： Not Technology-Specific (Undetermined)

常见后果

观察示例

潜在缓解措施

Phases : Architecture and Design
Design proper policies for hardware register access from software.
Phases : Implementation
Ensure that access control policies for register access are implemented in accordance with the specified design.

检测方法

Manual Analysis

This is applicable in the Architecture phase before implementation started. Make sure access policy is specified for the entire memory map. Manual analysis may not ensure the implementation is correct.
有效性 : Moderate

Manual Analysis

Registers controlling hardware should have access control implemented. This access control may be checked manually for correct implementation. Items to check consist of how are trusted parties set, how are trusted parties verified, how are accesses verified, etc. Effectiveness of a manual analysis will vary depending upon how complicated the interface is constructed.
有效性 : Moderate

Simulation / Emulation

Functional simulation is applicable during the Implementation Phase. Testcases must be created and executed for memory mapped registers to verify adherence to the access control policy. This method can be effective, since functional verification needs to be performed on the design, and verification for this weakness will be included. There can be difficulty covering the entire memory space during the test.
有效性 : Moderate

Formal Verification

Formal verification is applicable during the Implementation phase. Assertions need to be created in order to capture illegal register access scenarios and prove that they cannot occur. Formal methods are exhaustive and can be very effective, but creating the cases for large designs may be complex and difficult.
有效性 : High

Automated Analysis

Information flow tracking can be applicable during the Implementation phase. Security sensitive data (assets) - for example, as stored in registers - is automatically tracked over time through the design to verify the data doesn't reach illegal destinations that violate the access policies for the memory map. This method can be very effective when used together with simulation and emulation, since detecting violations doesn't rely on specific scenarios or data values. This method does rely on simulation and emulation, so testcases must exist in order to use this method.
有效性 : High

Architecture or Design Review

Manual documentation review of the system memory map, register specification, and permissions associated with accessing security-relevant functionality exposed via memory-mapped registers.
有效性 : Moderate

Fuzzing

Perform penetration testing (either manual or semi-automated with fuzzing) to verify that access control mechanisms such as the memory protection units or on-chip bus firewall settings adequately protect critical hardware registers from software access.
有效性 : Moderate

漏洞映射说明

依据 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
备注 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

相关攻击模式

参考资料

REF-1340

Hackatdac19 csr_regfile.sv
https://github.com/HACK-EVENT/hackatdac19/blob/619e9fb0ef32ee1e01ad76b8732a156572c65700/src/csr_regfile.sv#L854:L857

REF-1341

The RISC-V Instruction Set Manual
Andrew Waterman, Yunsup Lee, Rimas Avižienis, David Patterson, Krste Asanović.
https://people.eecs.berkeley.edu/~krste/papers/riscv-privileged-v1.9.1.pdf

REF-1345

csr_regfile.sv
Florian Zaruba, Michael Schaffner, Andreas Traber.
https://github.com/openhwgroup/cva6/blob/7951802a0147aedb21e8f2f6dc1e1e9c4ee857a2/src/csr_regfile.sv#L868:L871

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