CWE-1298
Hardware Logic Contains Race Conditions
2020-08-20
00h00 +00:00
00h00 +00:00
指定 CWE 通知
随时了解指定 CWE 的变更。
名称: Hardware Logic Contains Race Conditions
A race condition in the hardware logic results in undermining security guarantees of the system.
基本信息
引入方式
Architecture and DesignImplementation
适用平台
编程语言
名称： Verilog (Undetermined)名称： VHDL (Undetermined)
技术
类： System on Chip (Undetermined)常见后果
| 影响范围 | 影响 | 可能性 |
|---|---|---|
| Access Control | Bypass Protection Mechanism, Gain Privileges or Assume Identity, Alter Execution Logic 注意： If timing errors occur in access control logic or finite state machines that are implemented in security sensitive flows, an attacker might exploit them to circumvent existing protections. |
潜在缓解措施
Phases : Architecture and DesignAdopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.
Phases : Implementation
Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.
漏洞映射说明
依据 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.备注 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
相关攻击模式
| CAPEC ID | 攻击模式名称 |
|---|---|
| CAPEC-26 | Leveraging Race Conditions
The adversary targets a race condition occurring when multiple processes access and manipulate the same resource concurrently, and the outcome of the execution depends on the particular order in which the access takes place. The adversary can leverage a race condition by "running the race", modifying the resource and modifying the normal execution flow. For instance, a race condition can occur while accessing a file: the adversary can trick the system by replacing the original file with their version and cause the system to read the malicious file. |
参考资料
REF-1115
FPGA designs with Verilog (section 7.4 Glitches)Meher Krishna Patel.
https://verilogguide.readthedocs.io/en/latest/verilog/fsm.html
REF-1116
Non-Blocking Assignments in Verilog Synthesis, Coding Styles that Kill!Clifford E. Cummings.
http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
REF-1394
dma.svhttps://github.com/HACK-EVENT/hackatdac21/blob/main/piton/design/chip/tile/ariane/src/dma/dma.sv
REF-1395
Fix for dma.svhttps://github.com/HACK-EVENT/hackatdac21/blob/cwe_1298_in_dma/piton/design/chip/tile/ariane/src/dma/dma.sv
提交记录
| 名称 | 组织 | 日期 | 发布日期 | Version |
|---|---|---|---|---|
| Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi | Intel Corporation | 4.2 |
修改记录
| 名称 | 组织 | 日期 | 备注 |
|---|---|---|---|
| CWE Content Team | MITRE | updated Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Relationships | |
| CWE Content Team | MITRE | updated Mapping_Notes | |
| CWE Content Team | MITRE | updated Demonstrative_Examples, References | |
| CWE Content Team | MITRE | updated Weakness_Ordinalities | |
| CWE Content Team | MITRE | updated Common_Consequences, Demonstrative_Examples, Description |
