CWE-1476 详情

The product uses a multi-manager shared bus architecture with an on-chip interconnect that speculatively propagates a request for a write transaction, but it does not ensure that the remaining steps required by the manager module to complete the request are fulfilled in a timely manner.

背景详情

引入方式

适用平台

编程语言

类： Not Language-Specific (Undetermined)

架构

名称： ARM (Undetermined)
类： Not Architecture-Specific (Undetermined)

技术

名称： Bus/Interface Hardware (Undetermined)
名称： Communication Hardware (Undetermined)
类： System on Chip (Undetermined)

常见后果

观察示例

潜在缓解措施

检测方法

Architecture or Design Review

有效性 : Opportunistic

Formal Verification

有效性 : High

Simulation / Emulation

有效性 : Moderate

漏洞映射说明

依据 : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
备注 : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

参考资料

REF-1585

Cut and Forward: Safe and Secure Communication for FPGA System on Chips
Francesco Restuccia, Ryan Kastner.
https://ieeexplore.ieee.org/document/9852740

REF-1586

Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgio Buttazzo.
https://ieeexplore.ieee.org/abstract/document/9114758

REF-1587

[AXI-REALM: A lightweight and modular interconnect extension for traffic regulation and monitoring of heterogeneous real-time SoCs
Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini.
https://ieeexplore.ieee.org/document/10546511

REF-1588

Safety verification of third-party hardware modules via information flow tracking
Andres Meza, Francesco Restuccia, Ryan Kastner, Jason Oberg.
https://kastner.ucsd.edu/wp-content/uploads/2022/08/admin/rage22-safety.pdf

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