CWE-1199 Kategoriedetails

CWE-1199

General Circuit and Logic Design Concerns
Draft
2020-02-24 +00:00
2023-06-29 +00:00
Benachrichtigungen für ein CWE
Bleiben Sie über alle Änderungen zu einem bestimmten CWE informiert.
Benachrichtigungen verwalten

Name: General Circuit and Logic Design Concerns

Weaknesses in this category are related to hardware-circuit design and logic (e.g., CMOS transistors, finite state machines, and registers) as well as issues related to hardware description languages such as System Verilog and VHDL.

CWE-Informationen

Hinweise zur Schwachstellen-Zuordnung

Begründung : This entry is a Category. Using categories for mapping has been discouraged since 2019. Categories are informal organizational groupings of weaknesses that can help CWE users with data aggregation, navigation, and browsing. However, they are not weaknesses in themselves.
Kommentar : See member weaknesses of this category.

Einreichung

Name Organisation Datum Veröffentlichungsdatum Version
CWE Content Team MITRE 2019-12-27 +00:00 2020-02-24 +00:00 4.0

Änderungen

Name Organisation Datum Kommentar
CWE Content Team MITRE 2020-06-25 +00:00 updated Relationships
CWE Content Team MITRE 2020-08-20 +00:00 updated Relationships
CWE Content Team MITRE 2023-01-31 +00:00 updated Relationships
CWE Content Team MITRE 2023-04-27 +00:00 updated Mapping_Notes
CWE Content Team MITRE 2023-06-29 +00:00 updated Mapping_Notes