CWE-1199 類別詳細資料

CWE-1199

General Circuit and Logic Design Concerns
2020-02-24 +00:00
Draft
2023-06-29 +00:00
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掌握特定 CWE 的任何變更。
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名稱: General Circuit and Logic Design Concerns

Weaknesses in this category are related to hardware-circuit design and logic (e.g., CMOS transistors, finite state machines, and registers) as well as issues related to hardware description languages such as System Verilog and VHDL.

CWE 資訊

漏洞對應備注

理由說明 : This entry is a Category. Using categories for mapping has been discouraged since 2019. Categories are informal organizational groupings of weaknesses that can help CWE users with data aggregation, navigation, and browsing. However, they are not weaknesses in themselves.
備註 : See member weaknesses of this category.

提交

名稱 機構 日期 發布日期 Version
CWE Content Team MITRE 2019-12-27 +00:00 2020-02-24 +00:00 4.0

修改記錄

名稱 機構 日期 備註
CWE Content Team MITRE 2020-06-25 +00:00 updated Relationships
CWE Content Team MITRE 2020-08-20 +00:00 updated Relationships
CWE Content Team MITRE 2023-01-31 +00:00 updated Relationships
CWE Content Team MITRE 2023-04-27 +00:00 updated Mapping_Notes
CWE Content Team MITRE 2023-06-29 +00:00 updated Mapping_Notes