CWE-1298 Detail

A race condition in the hardware logic results in undermining security guarantees of the system.

A race condition in logic circuits typically occurs when a logic gate gets inputs from signals that have traversed different paths while originating from the same source. Such inputs to the gate can change at slightly different times in response to a change in the source signal. This results in a timing error or a glitch (temporary or permanent) that causes the output to change to an unwanted state before settling back to the desired state. If such timing errors occur in access control logic or finite state machines that are implemented in security sensitive flows, an attacker might exploit them to circumvent existing protections.

Modes Of Introduction

Architecture and Design
Implementation

Applicable Platforms

Language

Name: Verilog (Undetermined)
Name: VHDL (Undetermined)

Technologies

Class: System on Chip (Undetermined)

Common Consequences

Potential Mitigations

Phases : Architecture and Design
Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.
Phases : Implementation
Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.

Vulnerability Mapping Notes

Rationale : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Comments : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Related Attack Patterns

References

REF-1115

FPGA designs with Verilog (section 7.4 Glitches)
Meher Krishna Patel.
https://verilogguide.readthedocs.io/en/latest/verilog/fsm.html

REF-1116

Non-Blocking Assignments in Verilog Synthesis, Coding Styles that Kill!
Clifford E. Cummings.
http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

REF-1394

dma.sv
https://github.com/HACK-EVENT/hackatdac21/blob/main/piton/design/chip/tile/ariane/src/dma/dma.sv

REF-1395

Fix for dma.sv
https://github.com/HACK-EVENT/hackatdac21/blob/cwe_1298_in_dma/piton/design/chip/tile/ariane/src/dma/dma.sv

Submission

Modifications