Modes d'introduction
Implementation : Such issues could be introduced during implementation of hardware design, since IP parameters and defaults are defined in HDL code and identified later during Testing or System Configuration phases.
Plateformes applicables
Langue
Name: Verilog (Undetermined)
Name: VHDL (Undetermined)
Technologies
Class: Not Technology-Specific (Undetermined)
Conséquences courantes
| Portée |
Impact |
Probabilité |
Confidentiality Integrity Availability Access Control | Varies by Context
Note: Degradation of system functionality, or loss of access control enforcement can occur. | |
Mesures d’atténuation potentielles
Phases : Architecture and Design
During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings.
Phases : Implementation
The default values of these security sensitive settings need to be defined as part of the design review phase.
Méthodes de détection
Automated Analysis
Use automated tools to test that values are configured per design specifications.
Notes de cartographie des vulnérabilités
Justification : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Commentaire : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
Modèles d'attaque associés
| CAPEC-ID |
Nom du modèle d'attaque |
| CAPEC-166 |
Force the System to Reset Values
An attacker forces the target into a previous state in order to leverage potential weaknesses in the target dependent upon a prior configuration or state-dependent factors. Even in cases where an attacker may not be able to directly control the configuration of the targeted application, they may be able to reset the configuration to a prior state since many applications implement reset functions. |
Références
REF-1356
fuse_mem.sv
https://github.com/HACK-EVENT/hackatdac21/blob/main/piton/design/chip/tile/ariane/src/fuse_mem/fuse_mem.sv#L14-L15 REF-1357
fix CWE 1221 in fuse_mem.sv
https://github.com/HACK-EVENT/hackatdac21/compare/main...cwe_1221_in_fuse_mem#diff-d7275edeac22f76691a31c83f005d0177359ad710ad6549ece3d069ed043ef21 REF-1437
acct_wrapper.sv
https://github.com/HACK-EVENT/hackatdac21/blob/65d0ffdab7426da4509c98d62e163bcce642f651/piton/design/chip/tile/ariane/src/acct/acct_wrapper.sv#L39 REF-1438
Bad Code acct_wrapper.sv
https://github.com/HACK-EVENT/hackatdac21/blob/65d0ffdab7426da4509c98d62e163bcce642f651/piton/design/chip/tile/ariane/src/acct/acct_wrapper.sv#L79C1-L86C16 REF-1439
Good Code acct_wrapper.sv
https://github.com/HACK-EVENT/hackatdac21/blob/062de4f25002d2dcbdb0a82af36b80a517592612/piton/design/chip/tile/ariane/src/acct/acct_wrapper.sv#L84
Soumission
| Nom |
Organisation |
Date |
Date de publication |
Version |
| Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi |
Intel Corporation |
2019-12-12 +00:00 |
2020-02-24 +00:00 |
4.0 |
Modifications
| Nom |
Organisation |
Date |
Commentaire |
| CWE Content Team |
MITRE |
2021-07-20 +00:00 |
updated Related_Attack_Patterns |
| CWE Content Team |
MITRE |
2021-10-28 +00:00 |
updated Common_Consequences |
| CWE Content Team |
MITRE |
2022-10-13 +00:00 |
updated Demonstrative_Examples |
| CWE Content Team |
MITRE |
2023-04-27 +00:00 |
updated Relationships |
| CWE Content Team |
MITRE |
2023-06-29 +00:00 |
updated Mapping_Notes |
| CWE Content Team |
MITRE |
2023-10-26 +00:00 |
updated Demonstrative_Examples, Description, References, Relationships |
| CWE Content Team |
MITRE |
2024-02-29 +00:00 |
updated Demonstrative_Examples |
| CWE Content Team |
MITRE |
2024-07-16 +00:00 |
updated Demonstrative_Examples, References |
| CWE Content Team |
MITRE |
2025-12-11 +00:00 |
updated Detection_Factors, Potential_Mitigations, Weakness_Ordinalities |