Détail du CWE-1224

The hardware design control register "sticky bits" or write-once bit fields are improperly implemented, such that they can be reprogrammed by software.

Modes d'introduction

Architecture and Design
Implementation : Such issues could be introduced during implementation of hardware design, since IP parameters and defaults are defined in HDL code and identified later during Testing or System Configuration phases.

Plateformes applicables

Langue

Name: Verilog (Undetermined)
Name: VHDL (Undetermined)

Technologies

Class: System on Chip (Undetermined)

Conséquences courantes

Mesures d’atténuation potentielles

Phases : Architecture and Design
During hardware design, all register write-once or sticky fields must be evaluated for proper configuration.

Méthodes de détection

Automated Analysis

Use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.

Notes de cartographie des vulnérabilités

Justification : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Commentaire : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Modèles d'attaque associés

Soumission

Modifications